A transistor typically comprises a channel, for instance as a channel layer or region, connecting a source and a drain region. A channel is provided with a gate contact, for controlling a current going through the channel between source and drain.
The skilled person knows that the amount of stress in the channel region needs to be controlled, as it is an important parameter defining the properties of the transistor device.
Typically, a strain relaxed buffer layer (SRB) is applied between the base substrate, e.g. a silicon substrate, and an active semiconductor layer which embodies the channel. Such a SRB layer is known to be an efficient stressor for a channel layer, for instance for a channel layer of a FINFET transistor device.
The inherent nature of these SRB layers is such that they comprise defects, for instance misfit dislocations, threading dislocations, twin defects etc. Such defects are unwanted for CMOS applications as they may for instance increase leakage current, degrade mobility and decrease yield of working devices.
Defect reduction techniques for SRB layers currently exist, but are costly and/or difficult in use. These techniques rely for instance in increasing thickness of the SRB layer and/or applying Aspect Ratio Trapping (ART) techniques.
Still, threading dislocation densities for SRB layers remain high, and have not been demonstrated to be lower than 105/cm2.
There exists a need for alternative stressor techniques for a channel layer of transistor devices.